Telecommunication system with transport protocol device for mixing asynchronous signaling traffic with TDM traffic on a TDM backbone

ABSTRACT

A telecommunications system comprises a plurality of servers interconnected by a TDM backbone and able to share a common channel or bandwidth. An arrangement for sending messages or files between said servers comprises a master node for sending a continuous stream of cells round the backbone, each cell having a header portion and a payload portion, and a plurality of downstream nodes which upon arrival of incoming cells insert information therein, read information therefrom, or allow the cells to pass thereby unaltered.

This invention relates to a telecommunications system, and moreparticularly to an arrangement for sending messages or files betweenservers in a system comprising a plurality of servers interconnected bya TDM backbone and able to share a common channel or bandwidth. Theinvention also relates to a device for implementing a TDM (Time DivisionMultiplex) based cell relay transport mechanism for high speedcommunications.

Telephony servers or MVIP (Multi-Vendor Integrated Protocol) serversinterconnected by high speed TDM (Time Division Multiplex) backbones arenow becoming available in the communications industry. One such systemis described in our co-pending Canadian patent application no. 2109534filed on Nov. 19, 1993. Applications of such distributed systems are:distributed PBX, Interactive Voice response systems, Video and voicemail systems, multimedia networks, Intelligent Switching Hubs,communication systems with fast messaging requirements such as hand-offsignaling in wireless applications and others.

When such systems are used in association with other Mitel devices, suchas the Voice/MVIP Interface circuit (VMIC), they allow theimplementation of a transport system that mixes time-slot and ATM cellstogether in the same TDM backbone (See our co-pending applicationreferred to above).

In such systems there is a need to establish a Common ChannelSignaling/Messaging solution between telephony servers (e.g., callcontrol data) as well as general data transfer (e.g., fax data).

Our co-pending Canadian patent application no. 2,058,654 described aMedia Access Control (MAC) mechanism that allows several serversconnected to the same ring to share a common channel or bandwidthavailable in the ring to send messages or files between each other. Thismechanism is known as a G-bus.

Existing TDM systems utilize bit oriented protocols such as HDLC orproprietary messaging to perform intermodule or interboard signaling.Other systems that are not TDM based and are used in LANs such as FDDIor token ring, utilize their own asynchronous protocols to perform MediaAccess Control mechanisms.

Existing signaling devices such as HDLC controllers are not designed fortransmission at high speeds. Some controllers today available in themarket operate up to 52 Mb/s. Other devices have throughput limitationsand cannot handle messages with transmission rates beyond some hundredsof Kb/s. Other similar schemes being announced in the market today areFDDI-2 (100 Mb/s) and IsoEthernet (16 Mb/s) technologies that allowisochronous and asynchronous data to be multiplexed together on to thesame physical TDM backbone.

The article entitled Implementing the Orwell Protocol over a Fibre-basedHigh-Speed ATM network, Electronic and Communication EngineeringJournal, Vol. 4, no. 6, December 1992, discloses and ATM-like protocolthat sends cells round a ring. Cells can be placed on or removed fromthe ring at nodes. However, this article does not disclose anarrangement that permits the transport of TDM traffic on the ring.

Accordingly the present invention provides a telecommunications systemcomprising a plurality of servers interconnected by a high speed TDMbackbone defining a plurality of timeslots, said servers being able toshare a common channel or bandwidth, a master node for sending acontinuous stream of cells carrying asynchronous data in the form offiles or control messages round the backbone, each said cell having aheader portion and a payload portion, and a plurality of downstreamnodes which upon arrival of incoming cells insert information therein,read information therefrom, or allow said cells to pass therebyunaltered, characterized in that a high-speed framer on said backbone isconnected to an interface device for time division multiplexeddelay-sensitive traffic and to a transport protocol circuit generatingsaid stream of cells and performing format, mapping and MAC functions tointerface said cells to said TDM backbone, and said interface devicegenerates control signals to control the transmission of cells from saidtransport protocol circuit to said framer so as to permit theco-existence of delay sensitive traffic from said interface device anddelay non-sensitive traffic from said transport protocol circuit on saidTDM backbone in a bandwidth-on-demand environment.

When the G-BUS protocol is implemented utilizing cell relay technology,signaling messages or general data of variable length can be transferredbetween different servers. Messages that have less than 48 bytes oflength can be transferred directly to the high speed TDM backbonewithout being segmented/reassembled. Messages or user data with morethan 48 bytes can utilize conventional off-the-shelf AAL (ATM AdaptationLayer) controllers available in the market to perform SAR (segmentationand reassembly) functions before being cell formatted.

The invention is generally implemented in the form on an integratedcircuit, known as a TPI (Transport Protocol IC) device.

The physical layer convergence procedure employed by the TPI deviceallows the users connected by the TDM ring to implement "bandwidth ondemand" functions when sharing the bandwidth with the VMIC device. As anexample, from the 155 Mb/s bandwidth available on the TDM ring (up to2430 time-slots), some applications may require 150 Mb/s for thetransport of voice and video while the remaining 5 Mb/s can utilize theG-BUS cell relay protocol for the transport of data or interservermessaging. In other applications, the user may reserve 150 Mb/s for datawhile 5 Mb/s can be reserved for voice/video. The bandwidth on demandcapabilities provided by this device, are simply controlled by the VMICinternal memories.

The present invention can increase the throughput of existing signalingsystems to the range 155 Mb/s while maintaining compatibility with cellrelay technology at the protocol level.

The invention will now be described in more detail, by way of exampleonly, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a distributed telephony server based onMVIP technology;

FIG. 2 is a block diagram of a system allowing ATM cells to be carriedover TDM backbones;

FIG. 3 is a diagram of a Transport Protocol Ring;

FIG. 4 is a diagram of the G-bus train format;

FIG. 5 is a diagram of the G-bus cell format; and

FIG. 6 is a block diagram of a TPI device.

Referring now to FIG. 1, MVIP servers 1 are interconnected by a TDMbackbone 2 carrying voice, video and data at speeds of up to 155 mb/s.Servers are connected to workstations 3 and video conferencing centers 4via DNIC or ISDN links 5. The servers 1 are also linked to an Ethernetconnection 6. Network access server 1a is linked to WAN 7 via n 64 kb/schannels. The invention permits the implementation of G-bus MAC protocolusing ATM cells over TDM backbone 2.

FIG. 2 depicts a hybrid TDM/ATM local environment showing a TPI devicein accordance with the invention. MVIP server 1 is connected to VMIC(Voice/Multimedia Interface Circuit) 10, which serves as an interfacedevice for time division multiplexed delay sensitive traffic and MSAC(Isochronous to packet Converter) device 11. VMIC 10 is connected to 155Mb/s TDM framer 12. TPI device 13, which has it own local CPU (CentralProcessing Unit) 14 is also connected to the Framer 12. MSAC 11 isconnected through external buffer 15 to host bus 16 and existing SAR(Segmentation and Reassembly) devices 17, also connected to TPI device13, which is shown in more detail in FIG. 6.

Referring now to FIG. 6, TPI device 13 comprises receive (RX) andtransmit (TX) G-bus state machines 30, 31 connected to respectivereceive and transmit FIFO memories 32, 33 associated with internalregisters 32a, 33a. FIFO memories 32, 33 are connected to existing SARdevices 17 and CPU interface 34.

Parallel input data is fed through input latch 35 to RX G-bus statemachine 30 and unit 36 consisting of address comparator 36a, CRC checker36b, and cell delineator 36c.

TX G-bus state machine is connected to CRC generator 37 and output latch38 from which parallel output data emerges. Timing control is providedby TPI general timing unit 39.

As shown in FIG. 2, TPI device 13 performs the format, mapping and MACfunctions necessary to interface the ATM cells with the TDM Backbone.

In FIG. 2, the TPI and the VMIC devices 13, 10 share the same parallel19.44 Mb/s bus 18 when connected to commercially available high speedserial to parallel/parallel to serial converters (e.g.; TranswitchSYN-155). The SYN-155 device will convert the internal 8 KHz basedbackplane at 19.44 MByte/s into a serial stream at 155 Mb/s which can beutilized in the formation of a high speed TDM ring.

The VMIC device 10 provides built-in time interchange circuits thatallow time-slot switching to be performed on channels to be transportedfrom the MVIP interface to the high speed TDM backbone and vice-versa.In addition to this capability, the VMIC device provides an internalbypass function from the parallel port input to the parallel port outputallowing unused time slots to be bypassed back to the ring.

To perform the above functions, the VMIC device implements timingsynchronization and memory capabilities to allow the user to programdata acquisition, switching or bypass functions of up to 2430 timeslotsin every 125 us. Since the VMIC's internal programmable memories arelocked to the 8 KHz and byte clock timing of the high speed frame 12,the device is capable of generating output control signals (CToO-3) thatare synchronized at byte level on the parallel port (up to 19.44MByte/s). These control signals have 64 Kb/s granularity and thereforecan be applied to the TPI device to control the transmission of cells onthe parallel port as well as to avoid data contention between the VMICand TPI devices when sharing the same TDM physical layer.

The transition of the VMIC's CTo signal applied to the TPI deviceinforms the instant in time that bytes containing G-BUS cells can bereceived and transmitted on to the parallel port. To facilitate theacquisition of cell boundaries in applications where the number oftime-slots allocated for signaling is not a multiple of an ATM cell size(53 bytes), an optional cell delineation circuit compatible to the ATMstandards can be enabled by the CPU. This method allows the TPI deviceto be independent of physical layer and avoids the extra circuitry togenerate pointers and counters.

The G-BUS Transport Protocol referred to above provides a fast messagingsystem with scalable bandwidth. The TPI 13 device implements the G-BUSstate machines utilizing cell relay technology. It allows scalablebandwidth to allow "bandwidth on demand" systems to be created and lowpass-through delay. The processing of the G-BUS state machines has to bedone within the bypass time of the VMIC device (around 15 μs). Roundtrip of messages around the ring has is done in less than 10 ms.

The transport protocol is configured in a logical ring, with nodesattached to the ring as shown in FIG. 3. When implementing the G-BUSwith cell relay technology, the ATM cell header is modified to attend tothe requirements of the protocol. In the ring system, shown in FIG. 3,one of the nodes 20 is the bus master (M), employing the TPI device inmaster mode. All other nodes are slave nodes 21 with their respectiveTPI devices 13 in slave mode.

In operation master node 20 sends out a continuous stream of empty cellstowards downstream nodes. Any node can fill the cells with informationor let it pass by, or it can read cells with information destined foritself, and tag a header to indicate that it has read the cell. Adelimiter field in the header indicates if a cell is empty or carriesdata.

The message size can be either limited to 48 bytes or be longer than 48bytes. For systems that require messages with no more than 48 bytes, theTPI device 13 does not require the addition of Segmentation andReassemble (SAR) devices and it provides internal buffers to receiveuser data before inserting it into the high speed backbone. For systemsrequiring data transfer or messages with more than 48 bytes, the TPIdevice provides an interface (e.g, UTOPIA BUS) to standard SAR devicesavailable in the market (ATM Adaptation Layer devices).

In the G-BUS protocol a train of cells starts at the master with a cellthat has an S (start) delimiter followed by a N (new) delimiter cell,and ends with an E (end) delimiter cell as shown in FIG. 4. Each node20, 21 can read cells addressed to itself, or it may append one or moredata cells to the end of the train by overwriting the E-cell andreattaching the E cell at the end. According to the G-BUS protocol, usercells that are appended at the end of the train are transferred to the"echo" group once they pass through the master (see example in FIG. 4).Only the master node can remove cells from the train. If a cell is readby the node, an ACK bit located in the cell header will be set to avoidthe cell being read more than once (the cell may rotate more than oncearound the ring). A priority mechanism may determine the maximum numberof cells to be appended by each station.

When the train returns to the master node, the master TPI device willre-assemble the train by deleting cells that have been around for asecond time (to assure each cell passed every node) and retransmittingthe resulting train back towards the downstream nodes.

G-bus cells hold 53 bytes and are divided into two parts: header andpayload. The header contains 5 bytes, the payload occupies 48 bytes.This cell format and size are similar the ATM cell format. Somedifferences exist in the use of the sub-fields in the header. Adheringto the ATM cell format will keep the option open to facilitate thetransmission of data and messages over a future ATM or DQDB network.

The G-BUS cell header contains the following fields:

    ______________________________________                                        DLM     4 bits         delimiter                                              DA      12 bits        destination address                                    SA      12 bits        source address                                         misc    4 bits         miscellaneous functions                                                       least significant bit: ACK                             HEC     8 bits         Header Error Control                                   ______________________________________                                    

The first four bits in the first header byte contain a delimiter. Thedelimiter is encoded as follows:

    ______________________________________                                        Bin.Code      Description                                                     ______________________________________                                        0000          idle cell (1) (carries no information)                          0001          start of train (S)                                              0010          end of train (E)                                                0011          start of new cells (N)                                          1000          user data cell (D) (carries valid user                                        data)                                                           ______________________________________                                    

A 24-bit address field is split into a destination address and sourceaddress of equal size, providing 4096 identifiers each. Only one bit inthe miscellaneous field is defined: the acknowledge ACK bit whichdetermines when a cell has been read by its destination.

The HEC field contains a CRC code calculated over the first four headerbytes. This protection prevents the cells from ending up at the wrongdestination in case of address corruption. For this purpose, thecontents of the header is only considered valid after CRC validation.Another function of the HEC field is to perform the cell delineationalgorithm defined by ATM standards (recommendation 1.432). Thisprocedure is required in applications where the number of time-slots inthe high speed backbone allocated for signaling is not a multiple of 53bytes. In this case, the boundaries of a G-BUS cell may transverse twosuccessive frames on the high speed backbone. The use of the celldelineation block is optional.

In order to insert cells, the slave node CPU places a cell in thetransmit FIFO of the TPI device. The TPI will monitor the incomingstream of cells, waiting for the EOT (End of Train) cell. When the EOTcell is detected, the slave will alter the EOT delimiter into a userdata delimiter, insert destination and source address, calculate theHEC, and append its data from the internal FIFO. After the user datacell has been written, the EOT cell will be appended at the end of thetrain.

In order to read a cell, the slave node will monitor the train for validDATA cells to check the header's CRC, check whether the ACK bit is reset(indicating that the cell has not yet been reset) and after clocking inthe data in the receiving FIFO interrupt the CPU for service.

The invention this implements a Common Channel Signaling (CCS) messagingscheme between distributed high speed systems. It allows the transportof asynchronous data over Time Division Multiplex (TDM) backbones attransmission rates up to 155 Mb/s, thus allowing a coexisting scenariowhere delay sensitive and non-sensitive traffic types can be transportedtogether. It also allows the implementation of "bandwidth on demand"systems of up to 155 Mb/s. Finally, it implements G-BUS media accesscontrol mechanism (MAC) over cell relay protocol and providesasynchronous cell transport capabilities for both message and generaldata (when used along with existing ATM Adaptation Layer devices).

We claim:
 1. A telecommunications system comprising a plurality ofservers interconnected by a high speed TDM backbone defining a pluralityof timeslots, said servers being able to share a common channel orbandwidth, a master node for sending a stream of cells capable ofcarrying asynchronous data in the form of control messages round thebackbone, each said cell having a header portion and a payload portion,a plurality of downstream nodes which upon arrival of incoming cellsinsert information therein, read information therefrom, or allow saidcells to pass thereby unaltered, a high-speed framer on said backbone isconnected to an interface device for time division miltiplexeddelay-sensitive traffic and to a transport protocol circuit generatingsaid stream of cells and performing format, mapping and MAC functions tointerface said cells to said TDM backbone, said interface devicegenerating control signals to control the transmission of cells fromsaid transport protocol circuit to said framer so as to permit theco-existence of time division multiplexed delay sensitive traffic fromsaid interface device and asynchronous delay non-sensitive signaling,traffic from said transport protocol circuit on said TDM backbone in abandwidth-on-demand environment.
 2. A telecommunications system asclaimed in claim 1, wherein said cells have a 48-byte payload portion.3. A telecommunications system as claimed in claim 2, wherein said nodesare arranged to tag said header portion after reading a said passingcell.
 4. A telecommunications system as claimed in claim 3, wherein saidcells contain a delimiter field in the header portion to indicatewhether they are empty or carry data in the payload portion.
 5. A systemas claimed in claim 1, wherein said transport protocol circuit comprisesinput and output data ports for receiving data from and outputting datato said framer; first and second FIFO memories for respectively storingdata to be sent to and a host bus; and first and second state machinesfor respectively processing said cells destined for and received fromsaid backbone.
 6. A system as claimed in claim 5, further comprising anaddress comparator, CRC checker and cell delineator connected to saidreceive state machine.
 7. A device as claimed in claim 6, wherein saidstate machines are connected to said respective data ports via latches.8. A device as claimed in claim 5, wherein said first and second FIFOmemories are connected to Segmentation and Reassembly (SAR) devices forsegmenting packets into cells and reassembling cells into packets.
 9. Adevice as claimed in claim 1, wherein said transport protocol circuitalso sends data files to said framer under the control of said controlsignals.